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july 2014 docid025637 rev 1 1 / 30 this is information on a product in full prod uction. www.st.com ld39200 2 a high psrr ultra low drop linear regulator with reverse current protection datasheet - production data features ? input voltage from 1.25 v to 6.0 v ? ultra low drop: 130 mv (typ.) at 2 a load ? 1% output accuracy at 25 c, 2% in full temperature range ? high psrr: 70 db at 1 khz ? reverse current protection ? 2 a guaranteed output current ? available in fixed and adjustable output voltage version from 0.5 v with 100 mv step ? power good ? internal current and ther mal limit ? operating junction temperature range: - 40 c to 125 c ? dfn6 (3 x 3 mm) and dfn8 (4 x 4 mm) packages applications ? telecom infrastructure ? medium power pol descripti on the ld39200 provides 2 a of maximum current with an input voltage range from 1.25 v to 6.0 v, and a typical dropout voltage of 130 mv. it is stable with ceramic capacitors on t he output (10 f). typical power supply rejection ratio is 70 db at 1 khz and starts to roll off at 20 khz. the enable logic control function puts the ld39200 in shutdown mode, reducing the total current consumption to 10 na (typ.). power good flag is avai lable on a dedicated pin. the device also includes reverse current protection, short - circuit constant current limit and thermal protection. typical applications are for telecom infrastructure and consumer.
contents ld39200 2 / 30 docid025637 rev 1 contents 1 block diagram ................................ ................................ .................. 3 2 pin configuration and description ................................ .................. 4 3 typical application ................................ ................................ .......... 6 4 maximum ratings ................................ ................................ ............. 7 5 electrical characteristics ................................ ................................ 8 6 application information ................................ ................................ 12 6.1 thermal and short - circuit protections ................................ .............. 12 6.2 output voltage setting for adj version ................................ ............ 12 6.3 enable pin ................................ ................................ ....................... 12 6.4 power good pin (pg) ................................ ................................ ...... 12 6.5 reverse current protection ................................ .............................. 13 7 typical performance characteristics ................................ ........... 14 8 package mechanical data ................................ ............................. 19 8.1 dfn6 (3 x 3 mm) mechanical data ................................ .................. 20 8.2 dfn8 (4 x 4 mm) mechanical data ................................ .................. 22 9 packaging mechanical data ................................ .......................... 24 9.1 dfn6 (3 x 3 mm) tape and reel mechanical data ............................ 24 9.2 dfn8 (4 x 4 mm) reel mechanical data ................................ ........... 26 10 ordering information ................................ ................................ ..... 28 11 revision history ................................ ................................ ............ 29
ld39200 block diagram docid025637 rev 1 3 / 30 1 block diagram figure 1 : block diagram
pin configuration and description ld39200 4 / 30 docid025637 rev 1 2 pin configuration and description figure 2 : pin configuration (top view) table 1: df n6 (3 x 3 mm) package pin description pin name pin number description in 6 input voltage gnd 3 ground en 5 enable pin. the device is in off state when this pin is pulled low adj/sense (1) 2 adjustable pin on adj version can be connected to external resistor divider to set the output voltage. output sense pin on the fixed version has to be connected to v out out 1 output voltage pg 4 power good gnd exposed pad exposed pad should be connected to gnd notes: (1) the output sense pin of the fixed version has to be connected to the output pin for proper operation. am13909v1
ld39200 pin configuration and description docid025637 rev 1 5 / 30 table 2: dfn8 (4 x 4 mm) package pin description pin name pin number description in (1) 7, 8 input voltage gnd 4 ground en 6 enable pin. the device is in off state when this pin is pulled low adj/sense (2) 3 adjustable pin on adj version can be connected to external resistor divider to set the output voltage. output sense pin on the fixed version has to be connected to v out out (3) 1, 2 output voltage pg 5 power good gnd exposed pad exposed pad should be connected to gnd notes: (1) both of input pins have to be connected together on the board. (2) the output sense pin of the fixed version has to be connected to the out pin for proper operation. (3) both of output pins have to be connected together on the board.
typical application ld39200 6 / 30 docid025637 rev 1 3 typical application figure 3 : ld39200 typical application schematic r1 and r2 are calculated according to the following formula: r1 = r2 x (v out / v adj . recommended value for c in and c out is 10 f. am13909v1 out gnd in en adj on off c i n r1 r2 c o u t l d 39200 c b y p ( op t io n al ) out gnd in en sense on off c i n l d 39200 c o u t pg pg
ld39200 maximum ratings docid025637 rev 1 7 / 30 4 maximum ratings table 3: absolute maximum ratings symbol parameter value unit v in input supply voltage - 0.3 to 7 v v adj adjustable voltage - 0.3 to 2 v v out /v sense output voltage/output sense voltage - 0.3 to 7 v i out output current internally limited a en enable pin voltage - 0.3 to 7 v pg power good pin voltage - 0.3 to 7 v p d power dissipation internally limited w esd charge device model 500 v human body model 2000 t j - op operating junction temperature - 40 to 125 c t j - max maximum junction temperature 150 c t stg storage temperature - 55 to 150 c absolute maximum ratings are those values beyond which damage to the device may occur. functional operation under these conditions is not implied. table 4: thermal data symbol parameter dfn6 (3 x 3 mm) dfn8 (4 x 4 mm) unit r thjc junction - to - case thermal resistance 10 4 c/w r thja junction - to - ambient thermal resistance 55 40
electrical characteristics ld39200 8 / 30 docid025637 rev 1 5 electrical characteristics (t j = 25 c, v in = v out +1 v; v out = v adj ; c in = 10 f; c out = 10 f; i out = 10 ma; v en = v in ) table 5: electrical characteristics, adjustable version symbol parameter test conditions min. typ. max. unit v in operating input voltage range 1.25 6.0 v v adj adjustable pin voltage 0.5 v adjustable pin voltage accuracy t j = 25 c - 1.0 1.0 % - 40 c < t j < 125 c - 2.0 2.0 i adj adjustable pin current - 40 c < t j < 125 c 100 na dv adj %/d vin static line regulation v out + 1 v < v in < 6.0 v; t j = 25 c 0.01 %/v - 40 c < t j < 125 c 0.2 dv adj %/d iout static load regulation 0 ma < i out < 2 a; t j = 25 c 0.1 %/a - 40 c < t j < 125 c 0.4 v drop dropout voltage (1) v in = 1.4 v; i out = 1 a; - 40 c < t j < 125 c 120 250 mv v in = 2.5 v; i out = 2 a; - 40 c < t j < 125 c 135 250 v in = 5.3 v; i out = 2 a; - 40 c < t j < 125 c 110 250 en output noise voltage v out = v adj ; f = 10 hz to 100 khz 45 v rms / v out en output noise voltage v in = v out + 0.4 v, i out = 700 ma; c in = c out = 10 uf, r2 = 10 k, r1 = (v out C 0.5) x 20 k, c byp = 470 nf 24 v rms svr supply voltage rejection v out = 1.8 v; v in = v out +0.5 v ; c out = 10 f; i out = 10 ma ; t j = 25 c; f = 1 khz 70 db v out = 1.8 v; v in = v out + 0.5 v ; c out = 10 f; i out = 10 ma ; t j = 25 c; f = 100 khz 50
ld39200 electrical characteristics docid025637 rev 1 9 / 30 symbol parameter test conditions min. typ. max. unit v out = 1.8 v; v in = v out + 0.5 v ; c out = 10 f; i out = 10 ma ; t j = 25 c; f = 500 khz 50 db v out = 1.8 v; v in = v out + 0.5 v ; c out = 10 f; i out = 10 ma ; t j = 25 c; f = 1 mhz 40 i q quiescent current i out = 0 a 100 a i out = 0 a; - 40 c < t j < 125 c 3 00 i out = 2 a; 1 ma i out = 2 a; - 40 c < t j < 125 c 3 shutdown current ven = 0, vin = 6 v 10 na i sc short - circuit current v out = 0 v 3.5 a i min minimum output current 0 a v en enable input logic low 1.25 v < v in < 6.0 v - 40 c < t j < 125 c 0.5 v enable input logic high 1.2 i en enable pin input current v en = v in ; 1.25 < v in < 6.0 v 10 na pg power good output threshold rising edge 0.92* v out v falling edge 0.8* v out power good output voltage low isink = 6 ma open drain output 0.4 t shdn thermal shutdown 170 c hysteresis 20 notes: (1) dropout voltage is the input - to - output voltage difference at which the output voltage is 100 mv below its nominal value; this specification does not apply to nominal output voltages below 1.2 v.
el ectrical characteristics ld39200 10 / 30 docid025637 rev 1 (t j = 25 c, v in = v out +1 v; c in = 10 f; c out = 10 f; i out = 10 ma; v en = v in ) table 6: electrical characteristics, fixed version symbol parameter test conditions min. typ. max. unit v in operating input voltage range 1.25 6.0 v v out output voltage accuracy t j = 25 c - 1.0 1.0 % - 40 c < t j < 125 c - 2.0 2.0 d vadj% / d vin static line regulation v out + 1 v < v in < 6.0 v; t j = 25 c 0.01 %/v - 40 c < t j < 125 c 0.1 d vadj% / d iout static load regulation 0 ma < i out < 2 a; t j = 25 c 0.05 %/a - 40 c < t j < 125 c 0.4 v drop dropout voltage v out = 3.3 v; i out = 2 a; - 40 c < t j < 125 c 130 250 mv en output noise voltage v out = 2.5 v; f = 10 hz to 100 khz; 40 v rms / v out svr supply voltage rejection v out = 1.8 v; v in = v out + 0.5 v ; c out = 10 f; i out = 10 ma; t j = 25 c; f =1 khz 70 db v out = 1.8 v; v in = v out + 0.5 v ; c out = 10 f; i out = 10 ma ; t j = 25 c; f = 100 khz 50 v out = 1.8 v; v in = v out + 0.5 v ; c out = 10 f; i out = 10 ma ; t j = 25 c; f = 500 khz 50 v out = 1.8 v; v in = v out + 0.5 v ; c out = 10 f; i out = 10 ma ; t j = 25 c; f = 1 mhz 40 i q quiescent current i out = 0 a 100 a i out = 0 a; - 40 c < t j < 125 c 3 00 i out = 2 a; 1 ma i out = 2 a; - 40 c < t j < 125 c 3 shutdown current ven = 0, vin = 6 v 50 na i sc short - circuit current v out = 0 v 3.5 a
ld39200 electrical characteristics docid025637 rev 1 11 / 30 symbol parameter test conditions min. typ. max. unit i min minimum output current 0 a v en enable input logic low 1.25 v < v in < 6.0 v - 40 c < t j < 125 c 0.5 v enable input logic high 1.2 i en enable pin input current v en = v in ; 1.25 < v in < 6.0 v 10 na pg power good output threshold rising edge 0.92* v out v falling edge 0.8* v out power good output voltage low isink = 6 ma open drain output 0.4 t shdn thermal shutdown 170 c hysteresis 20
application information ld39200 12 / 30 docid025637 rev 1 6 application information 6.1 thermal and short - circuit protections the ld39200 is self - protected from short - circuit conditions and overtemperature. when the output load is higher than the one supported by the device, the output current rises until the limit of typically 3.5 a is reached; at this point the current is kept constant even when the load impedance is zero. the thermal protection acts when the junction temperature reaches 170 c. the ic enters the shutdown s tatus. as soon as the junction temperature falls again below 150 c the device starts working again. in order to calculate the maximum power the device can dissipate, keeping the junction temperature below t j - op , the following formula is used: equation 1 6.2 output voltage setting for adj version in the adjustable version, the output voltage can be set from 0.5 v up to the input voltage minus the volta ge drop across the pass transistor (dropout voltage), by connecting a resistor divider between the adj pin and the output, allowing remote voltage sensing. the resistor divider can be selected using the following equation: equation 2 6.3 enable pin the ld39200 features an enable function. when the en voltage is higher than 1.2 v the device is on, and if it is lower than 0.5 v the device is off. in shutdown mode, the total current consumption is 10 na (typ). the en pin does not have an internal pull - up, therefore it cannot be left floating if it is not used. 6.4 power good pin (pg) some applications require a flag showing that the output voltage is in the correct range. power good threshold depends on the output voltage. when the output voltage is higher than 0.92*v out(nom) , the pg pin goes to high impedance. if the output voltage is below 0.80*v out(n om) the pg pin goes to low impedance. if the device works well, the pg pin is at high impedance.
ld39200 application information docid025637 rev 1 13 / 30 6.6 reverse current protection the device avoids the reverse curr ent to flow from the output to the input during any operating condition (en=0 or en=1, v in >v out +v drop ). during fast turn - on/off this function prevents a big current from flowing to the input. moreover it is used to avoid the reverse current to flow from th e output pin to the input one, when other power supplies, providing a voltage higher than the input voltage, are connected to the output pin. if a power supply, providing a voltage lower than ldo output voltage, is connected to out pin, ldo works in curren t protection, causing high power dissipation inside the device. when the device is disabled (en=low) and v out >0 v, a small current (few a) is sunk from the out pin.
typical performance characteristics ld39200 14 / 30 docid025637 rev 1 7 typical performance characteristics (the following plots are referred to the typical application circuit and, unless otherwise noted, at t a = 25 c) figure 4 : dropout voltage vs temperature (vin = 1.3 v, iout = 1 a) figure 5 : dropout voltage vs temperature (vin = 1.4 v, iout = 1 a) figure 6 : dropout voltage vs temperature (vin = 1.4 v, iout = 2 a) figure 7 : dropout voltage vs temperature (vin = 1.5 v, iout = 1 a) 0 50 1 0 0 1 5 0 2 0 0 2 5 0 - 40 - 25 0 25 55 85 1 2 5 m v t e m pe r a t u r e o c am13910v1 am13913v1 0 50 100 150 200 250 - 40 - 25 0 25 55 85 125 m v t e m pe r atu r e o c am13912v1 0 50 100 150 200 250 300 350 400 450 500 - 40 - 25 0 25 55 85 125 m v t e m pe r atu r e o c am139 1 1v1 0 50 100 150 200 250 - 40 - 25 0 25 55 85 125 m v t e m pe r atu r e o c
ld39200 typical performance characteristics docid025637 rev 1 15 / 30 figure 8 : dropout voltage vs temperature (vin = 1.5 v, iout = 2 a) figure 9 : dropout voltage vs temperature (vin = 2.5 v, iout = 1 a) figure 10 : dropout voltage vs temperature (vin = 2.5 v, iout = 2 a) figure 11 : reference voltage vs temperature (vin = 1.5 v, iout = 10 ma) figure 12 : quiescent current vs temperature (vin = 1.5 v, iout = 0 ma) figure 13 : quiescent current vs temperature (vin = 1.5 v, iout = 2 a) am13915v1 0 20 40 60 80 100 120 140 - 40 - 25 0 25 55 85 125 m v t e m pe r atu r e o c am13917v1 0. 4 5 0. 4 7 0. 4 9 0. 5 1 0. 5 3 0. 5 5 - 4 0 - 2 5 0 2 5 5 5 8 5 1 2 5 v ad j [ v ] t e m pe r a t u r e o c am13919v1 0 0 . 2 0 . 4 0 . 6 0 . 8 1 1 . 2 1 . 4 1 . 6 1 . 8 2 - 4 0 - 2 5 0 2 5 5 5 8 5 12 5 q u i e sc en t c u rr en t [ m a ] t e m pe r a t u r e o c am13916v1 0 50 100 150 200 250 300 -40 -25 0 25 55 85 125 m v t e m pera t ure o c am13918v1 0 0 . 0 5 0 . 1 0 . 1 5 0 . 2 0 . 2 5 0 . 3 - 4 0 - 2 5 0 2 5 5 5 8 5 12 5 q u i e sc ent c u rr en t [ m a ] t e m pe r a t u r e o c am13914v1 0 50 100 150 200 250 300 350 400 450 500 - 40 - 25 0 25 55 85 125 m v t e m pe r atu r e o c
typical performance characteristics ld39200 16 / 30 docid025637 rev 1 figure 14 : quiescent current vs output current figure 15 : line regulation vs temperature ( 1.5 v vin 6 v, iout = 10 ma) figure 16 : load regulation vs temperature ( vin = 1.5 v, 0 < iout < 2 a ) figure 17 : svr vs frequency figure 18 : noise spectral density (no cbyp) figure 19 : noise spectral density (cbyp = 470 nf) am13924v1 0 . 0 1 . 0 2 . 0 3 . 0 4 . 0 5 . 0 6 . 0 7 . 0 8 . 0 9 . 0 10 . 0 1 0 10 0 100 0 1000 0 10000 0 e n [ u v/s q r t (h z ) ] f [ h z ] v i n = 1 . 6 v v o u t = 1 . 2 v c b p = 470n f i l o a d = 0 . 7 a v i n = 3 . 7 v v o u t = 3 . 3 v c b p = 470n f i l o a d = 0 . 7 a v i n = 5 . 4 v v o u t = 5 . 0 v c b p = 470n f i l o a d = 0 . 7 a am13922v1 0 . 0 1 0 .0 2 0 .0 3 0 .0 4 0 .0 5 0 .0 6 0 .0 7 0 .0 8 0 .0 9 0 .0 1 0 0.0 1 0 0 1 0 00 1 0 000 1 0 00 0 0 1 0 00 0 00 sv r [d b] f [ h z ] v in = 2. 3 v + v r i p p l e v in = 4. 0 v + v r i p p l e am13920v2 0 0 . 2 0 . 4 0 . 6 0 . 8 1 1 . 2 1 . 4 0 1 10 1 0 0 5 0 0 1 0 00 1 2 50 1 5 00 1 7 50 2 0 00 q u i esce n t c u rr e n t [ a ] o u t pu t c u rr e n t [ m a ] am13923v1 0 . 0 1 . 0 2 . 0 3 . 0 4 . 0 5 . 0 6 . 0 7 . 0 8 . 0 9 . 0 10 . 0 1 0 10 0 100 0 1000 0 10000 0 e n [ u v/s q r t ( h z ) ] f [ h z ] v i n = 1 . 6 v v o u t = 1 . 2 v c b p = 0 i l o a d = 0 . 7 a v i n = 3 . 7 v v o u t = 3 . 3 v c b p = 0 i l o a d = 0 . 7 a v i n = 5 . 4 v v o u t = 5 . 0 v c b p = 0 i l o a d = 0 . 7 a am13921v1 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 - 40 - 25 0 25 55 85 125 load r egu l a t i on [ % / a ] t e m pe r atu r e o c am13920v1 0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1 - 40 - 25 0 25 55 85 125 l i ne r egu l a t i on [ % / v ] t e m pe r atu r e o c
ld39200 typical performance characteristics docid025637 rev 1 17 / 30 figure 20 : stability plan figure 21 : enable startup, vin = 1.25 v, iout = 2 a figure 22 : enable startup, vin = 6 v, i out = 2 a figure 23 : enable startup, no cbyp figure 24 : enable startup, cbyp = 470 nf figure 25 : line transient gipg080420141552m t v e n v ou t v in = 3.7 v , v out = 3.3 v , v en = from 0 to 2 v , i out = 100 ma, c in = c out = 10 f , c byp = 470 nf gipg080420141423m t v i n v e n i ou t v ou t v i n v e n i ou t v ou t v in = 6 v , v en = from 0 to v in , i out = 1 a, v out = v ref , c in = c out = 10 f , c byp = 0 nf gipg080420141550m t v e n v ou t v in = 3.7 v , v en = from 0 to 2 v , i out = 100 ma, v out = 3.3 v , c in = c out = 10 f , c byp = 0 nf am13925v1 0 . 0 1 0 . 1 1 1 0 0 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 e s r @ 1 0 0 k h z [ ] c o u t [ f ] ( n o m i n a l v a l u e ) s t a b i l i t y a r e a gipg140420141401m t v i n v ou t v in = v en = from 1.5 to 5.5 v , i out = 10 ma, n o c in = c out = 10 f , t rise = t f al l = 10 s gipg080420141417m t v i n v e n i o u t v o u t v in = 1.25 v , v en = from 0 to v in , i out = 2 a, v out = v adj , c in = c out = 10 f , c byp = 0 nf
typical performance characteristics ld39200 18 / 30 docid025637 rev 1 figure 26 : load transient, no cbyp figure 27 : load transient, cbyp = 470 nf gipg140420141405m t v i n v ou t v in = 3.7 v , v out = 3.3 v , i load = 10 m a to 2 a, c byp = 470 nf gipg140420141403m t v i n v ou t v in = 3.7 v , v out = 3.3 v , i load = 10 m a to 2 a, c byp = 0 nf
ld39200 package mechanical data docid025637 rev 1 19 / 30 8 package mechanical data in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions and product status are available at: www.st.com. ecopack ? is an st trademark.
package mechanical da ta ld39200 20 / 30 docid025637 rev 1 8.1 dfn6 (3 x 3 mm) mechanical data figure 28 : dfn6 (3 x 3 mm) drawings
ld39200 package mechanical data docid025637 rev 1 21 / 30 table 7: dfn6 (3 x 3 mm) mechanical data dim. mm min. typ. max. a 0.80 1 a1 0 0.02 0.05 a3 0.20 b 0.23 0.45 d 2.90 3 3.10 d2 2.23 2.50 e 2.90 3 3.10 e2 1.50 1.75 e 0.95 l 0.30 0.40 0.50 figure 29 : dfn6 (3 x 3 mm) footprint (all dimensions are in mm)
package mechanical data ld39200 22 / 30 docid025637 rev 1 8.2 dfn8 (4 x 4 mm) mechanical data figure 30 : dfn8 (4 x 4 mm) drawing
ld39200 package mechanical data docid025637 rev 1 23 / 30 table 8: dfn8 (4 x 4 mm) mechanical data dim. mm min. typ. max. a 0.80 0.90 1 a1 0 0.02 0.05 a3 0,20 b 0.23 0.30 0.38 d 3.90 4 4.10 d2 2.82 3 3.23 e 3.90 4 4.10 e2 2.05 2.20 2.30 e 0.80 l 0.40 0.50 0.60 figure 31 : dfn8 (4 x 4 mm) footprint (all dimensions are in mm)
packaging mechanical data ld39200 24 / 30 docid025637 rev 1 9 packaging mechanical data 9.1 dfn6 (3 x 3 mm) tape and reel mechanical data figure 32 : dfn6 (3 x 3 mm) tape
ld39200 packaging mechanical data docid025637 rev 1 25 / 30 figure 33 : dfn6 (3 x 3 mm) reel table 9: dfn6 (3 x 3 mm) tape and reel mechanical data dim. mm min. typ. max. a0 3.20 3.30 3.40 b0 3.20 3.30 3.40 k0 1 1.10 1.20
packaging mechanical data ld39200 26 / 30 docid025637 rev 1 9.2 dfn8 (4 x 4 mm) reel mechanical data figure 34 : dfn8 (4 x 4 mm) tape (all dimensions are in mm)
ld39200 packaging mechanical data docid025637 rev 1 27 / 30 figure 35 : dfn8 (4 x 4 mm) reel table 10: dfn8 (4 x 4 mm) reel mechanical data dim. mm min. typ. max. a 330 c 12.8 13.0 13.2 d 20.2 n 60 t 22.4 a d note: drawing not in scale c n t
ordering information ld39200 28 / 30 docid025637 rev 1 10 ordering information table 11: order codes dfn6 (3 x 3 mm) dfn8 (4 x 4 mm) output voltage ld39200dpur adj LD39200PU33R 3.3 v
ld39200 revision history docid025637 rev 1 29 / 30 11 revision history table 12: document revision history date revision changes 28 - jul - 2014 1 initial release.
ld39200 30 / 30 docid025637 rev 1 important notice C please read carefully stmicroelectronics nv and its subsidiaries (st) reserve the right to make changes, corrections, enhancements, modifications , and improvements to st products and/or to this document at any time without notice. purchasers should obtain the latest relevant information on st products before placing orders. st products are sold pursuant to sts terms and conditions of sale in place at the time of or der acknowledgement. purchasers are solely responsible for the choice, selection, and use of st products and s t assumes no liability for application assistance or the design of purchasers products. no license, express or implied, to any intellectual property right is granted by st herein. resale of st products with provisions different from the information se t forth herein shall void any warranty granted by st for such product. st and the st logo are trademarks of st. all other product or service names are the property of their respective owners. information in this document supersedes and replaces information previously supplied in any prior versions of this document. ? 2014 stmicroelectronics C all rights reserved

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